Signal delay circuit and signal delay method

ABSTRACT

A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a signal delay circuit and a signaldelay method, and particularly relates to a signal delay circuit and asignal delay method, which mix delay signals with different delayamount.

2. Description of the Prior Art

FIG. 1 illustrates a prior art signal delay circuit. As shown in FIG. 1,the signal delay circuit 100 includes a plurality of continuous delaystages 101-109. The delay stage 101 delays an input signal IN togenerate a delay signal DS₁, and the delay stage 103 delays the delaysignal DS1 from a previous delay stage to generate a delay signal DS₂That is, the outputs of each delay stage has different delay amountsfrom the input signal IN. After that, the signal delay circuit utilizesa multiplexer 111 to select one of the delay signals DS₁, DS₂ . . .DS_(n-1), DS_(n) as the output signal OUT. However, complicated designfor the multiplexer 111 is needed in this structure. Also, some delaywill be caused to the signals. Furthermore, higher accuracy for signalsis needed since speed of modern electronic devices largely increases.Therefore, the signal delay circuit 100 needs more delay stages to reachsuch requirement. Thereby the circuit region increases and thecomplexity for controlling the signal delay circuit 100 goes up as well.

In some signal delay circuits, a plurality of multiplexers are utilizedas delay stages, and a plurality of control signals are applied thereonto select. However, more than two output terminals and more than twomultiplexers are needed for this structure. Accordingly, more circuitregion is needed and hard to be controlled. Besides, such structurecauses more input loading.

Therefore, a signal delay circuit and a signal delay method are neededto improve above-mentioned problems.

SUMMARY OF THE INVENTION

One objective of the present application is to provide a signal delaycircuit and a signal delay method with low input loading and smallercircuit region.

One embodiment of the present invention discloses a signal delaycircuit, comprising: a first delay stage, for delaying a first inputsignal to generate a first delay signal; and a second delay stage, forcooperating with part of delay units of the first delay stage to delaythe first delay signal to generate a second delay signal; wherein thesignal delay circuit can selectively enable the delay units of the firstdelay stage or the second delay stage, wherein the signal delay circuitmixes the first delay signal and the second delay signal to generate afirst mixed signal when the first delay stage and the second delay stageare both enabled.

Another embodiment of the present invention discloses a signal delaymethod, for a signal delay circuit including a first delay path and asecond delay path, wherein the first delay path and the second delaypath share at least one delay unit. The signal delay method comprises:utilizing the first delay path to delay a first input signal to generatea first delay signal; utilizing the second delay path to delay the firstinput signal to generate a second delay signal; and mixing the firstdelay signal and the second delay signal to generate a first mixedsignal.

In view of above-mentioned embodiments, the signal delay circuitaccording to the present invention can have smaller input and outputloading. Additionally, different mixed signals can be utilized toperform fine tune to obtain more accurate clock signals, besidesutilizing each delay stage to perform coarse tune. Moreover, delay forcoarse tune and fine tune have better adjusting linearity since the samedelay stage(s) is/are utilized to perform both the fine tune and coarsetune.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a prior art signal delay circuit.

FIG. 2 is a circuit diagram illustrating a signal delay circuitaccording to one embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating the operation for the signaldelay circuit shown in FIG. 2.

FIG. 4-FIG. 7 are extended embodiments for the embodiment shown in FIG.2.

FIG. 8 illustrates a signal delay method according to an embodiment ofthe present invention.

DETAILED DESCRIPTION

Certain terms are used throughout the description and following claimsto refer to particular components. As one skilled in the art willappreciate, electronic equipment manufacturers may refer to a componentby different names. This document does not intend to distinguish betweencomponents that differ in name but not function. In the followingdescription and in the claims, the terms “include” and “comprise” areused in an open-ended fashion, and thus should be interpreted to mean“include, but not limited to . . . ”. Also, the term “couple” isintended to mean either an indirect or direct electrical connection.Accordingly, if one device is coupled to another device, that connectionmay be through a direct electrical connection, or through an indirectelectrical connection via other devices and connections.

FIG. 2 is a circuit diagram illustrating a signal delay circuitaccording to one embodiment of the present invention. AS shown in FIG.2, the signal delay circuit 200 includes a first delay stage 201, asecond delay stage 203 and a third delay stage 205. It should be notedthat although FIG. 2 depicts three delay stages, but it does not mean tolimit the number of delay stages. The number of delay stages can be moreor less than three. In FIG. 2, the first delay stage 201 delays theinput signal IN to generate DS₁ at the output terminal OUT. The seconddelay stage 203 cooperates with part of the first delay stage 201 todelay the input signal IN to generate DS₂ at the same output terminalOUT. Similarly, the third delay stage 205 cooperates with part of thefirst delay stage 201 and part of the second delay stage 203 to delaythe input signal IN to generate DS₃ at the same output terminal OUT. Thedetail operation for generating delay signals DS₁, DS₂ and DS₃ will bedescribed as below.

In one embodiment, the first delay stage 201 includes delay units 202,204, and the second delay stage 203 includes delay units 206, 208 and210. The input terminals of the delay unit 202 and the delay unit 206receive the input signal IN. The input terminal of the delay unit 204can receive outputs of the delay units 202 and 210. The input terminalof the delay unit 208 receives the output of the delay unit 206, and theinput terminal of the delay unit 210 receives the output of the delayunit 208. Similarly, the third delay stage 205 includes delay units 206,208 and 210, and the arrangement thereof is the same as which of thesecond delay stage 203, this is omitted for brevity here.

FIG. 3 is a schematic diagram illustrating the operation for the signaldelay circuit shown in FIG. 2. As shown in FIG. 3, the delay signal DS₁is generated by path 1, which has an order of: delay unit 202 to 204,and then to the output terminal OUT. The delay signal DS₂ is generatedby path 2, which has an order of: delay unit 206 to 208, 210, 204 andthen to the output terminal OUT. Similarly, the delay signal DS₃ isgenerated bypath 3, which has an order of: delay unit 206 to 212, 214,216, 210, 204 and then to the output terminal OUT. That is, the delaysignal CS₁ is generated by only the first delay stage 201, the delaysignal CS₂ is generated by the second delay stage 203 with part of thefirst delay stage 201 (the delay unit 204). Also, the delay signal CS₃is generated by the third delay stage 205 with part of the second delaystage 203 (delay units 206 and 210) and part of the first delay stage201 (the delay unit 204). It should be noted, in this embodiment, thedelay unit is implemented by an inverter and the signal delay circuit200 is designed that the input signal IN and the output signal OUT donot have opposite phases. Accordingly, the first delay stage 201includes only two delay units 202 and 204, but the second delay stage203 and the third delay stage 205 both have three delay units. However,the first delay stage 201 can have three delay stages if the item thatthe phases are opposite or not is not concerned. Besides, the delay unitcan be implemented by other devices, and the arrangement and the numberthereof will be different corresponding to used devices.

The signal delay circuit according to the present invention not only cangenerate delay signals with different delay amounts via different pathsbut also can generate mixed signals with different delay amount viacombining more than two paths. Take the embodiment shown in FIG. 2 forexample, DS₁ and DS₂ will be combined to generate a first mixed signalMS₁ if path 1 and path 2 are combined. The delay amount of the firstmixed signal MS₁, which is named first mixed delay amount here, isbetween the delay amounts of DS₁ and DS₂. The value thereof can becomputed by mathematical function such as interpolation. The detailsteps of how to compute MS₁ based on DS₁, DS₂ are well known for personsskilled in the art, thus is omitted for brevity here. Similarly, if path1, path 2, and path 3 are combined, DS₁, DS₂ and DS₃ can be combined togenerate a mixed signal. Also, a different mixed signal can be generatedif path 3 is combined with one of path 1 and path 2.

The signal delay circuit of the present invention can have otherarrangement besides the delay stage arrangement shown in FIG. 2 and FIG.3. FIG. 4-FIG. 6 are extended embodiments for the embodiment shown inFIG. 2. It should be noted that the first delay stage is symbolized asD₁ and the second delay stage is symbolized as D₂ . . . in followingembodiments for brevity. In the embodiment shown in FIG. 4, the firstdelay stage 401 and the second delay stage 403 can be utilized togenerate delay signals DS₁, DS₂ or mix delay signals DS₁, DS₂ togenerate a mixed signal MS₁, as above-mentioned description. Similarly,the third delay stage 405 and the fourth delay stage 407 can be utilizedto generate delay signals DS₃, DS₄ or mix delay signals DS₃, DS₄ togenerate a mixed signal MS₂. The signals from two sides can be furthermixed to generate a new mixed signal. For example, a new mixed signalMS₃ can be generated via mixing the mixed signal MS₁ with the delaysignal DS₃, and a new mixed signal MS₄ can be generated via mixing themixed signal MS₁ with the delay signal DS₄. The relation between thedelay signals DS₁, DS₂, and mixed signals MS₁, MS₃ and MS₄ can be shownas FIG. 4. It should be noted that, the mixed signal MS₁ generated fromthe delay stages 401, 403 and the delay signals DS₃ and DS₄ generatedfrom the delay stages 405, 407 are taken for example. However, if themixed signal MS₁ is replaced with the mixed signal MS₂ generated fromthe delay stages 405, 407, and delay signals DS₃, DS₄ are replaced withdelay signals DS₁ and DS₂ generated from the delay stages 401, 403, thesignals still have the same relation.

In one embodiment, if the delay amount of the third delay stage 405 isdesigned to be the same with which of the first delay stage 401, and thedelay amount of the fourth delay stage 407 is designed to be the samewith which of the second delay stage 403, then DS₃ will be the same asDS₁, and DS₂ will be the same as DS₄. In this case, only one of thefirst delay stage 401 and the third delay stage 405 is enabled, or bothare enabled, will cause the same situation. That is, generate DS₁ at theoutput terminal OUT. Similarly, only one of the second delay stage 403and the fourth delay stage 407 is enabled, or both are enabled, willcause the same situation. That is, generate DS₂ at the output terminalOUT.

The signal delay circuit of the present invention is not limited to thesymmetrical structure shown in FIG. 4, which has symmetric delay stagesat both sides. In FIG. 5, the signal delay circuit 500 does not includethe fourth delay stage 407 shown in FIG. 4. The operation for the signaldelay circuit 500 shown in FIG. 5 is similar with the signal delaycircuit 400 shown in FIG. 4. The first delay stage 401 and the seconddelay stage 403 can be utilized to generate delay signals DS₁, DS₂ orthe mixed signal MS₁. The mixed signal MS₁ and the delay signal DS₃ canbe mixed to generate the mixed signal MS₂. As above-mentioned, if thedelay amount of the third delay stage 405 is adjusted to be the same aswhich of the first delay stage 401, DS₃ will be the same as DS₁. Also,if the first delay stage 401 and the third delay stage 405 are bothenabled but the second delay stage 403 is disabled, DS₁ will begenerated at the output terminal OUT. Similarly, if the delay amount ofthe third delay stage 405 is adjusted to be the same as which of thedelay signal DS₂, DS₃ will be the same as DS₂. In this case, if thesecond delay stage 403 and the third delay stage 405 are both enabledbut part of the delay units of the first delay stage 401 is disabledsuch that DS₁ is not generated, DS₂ will be generated at the outputterminal OUT.

Moreover, the signal delay circuit of the present invention can receivesdifferent input signals and outputs delay signals with more variation.In FIG. 6, the signal delay circuit 600 includes first to eighth delayunits 602-612. The first to fourth delay units 602-608 receive the firstinput signal IN₁, and the fifth to eighth delay units 612-616 receivethe second input signal IN₂. As above-mentioned description, first tofourth delay units 602-608 can generate delay signals DS₁, DS₂, DS₃, DS₄and mixed signals MS₁ (DS₁+DS₂), MS₂ (DS₃+DS₄) , MS₃(MS₁+DS₃),MS₄(MS₁+DS₄). Similarly, fifth to eighth delay units 610-616 cangenerate delay signals DS_(S), DS₆, DS₇, DS₈ and mixed signals MS₅(DS₅+DS₆), MS₆ (DS₇+DS₈), MS₇ (MS₅+DS₇), MS₈(MS₅+DS₈). Signals of oneside can be mixed with signals with the other side to generate a newmixed signal at the output terminal OUT. For example, a new mixed signalcan be generated via mixing MS₄ and MS₇.

In one embodiment, the delay amounts of the first, the third, the fifthand the seventh delay units 602, 606, 610 and 614 are set to be thesame, and the delay amounts of the second, the fourth, the sixth and theeighth delay units 604, 608, 612 and 616 are set to be the same. In thiscase, DS₁=DS₃=DS₅=DS₇=DS₂=DS₄=DS₆=DS₈ MS₁=MS₂=MS₅=MS₆, MS₃=MS₇, MS₄=MS₈.The relations for each signal can be shown as FIG. 7. In FIG. 7, MS₉ isgenerated via mixing MS₃ and DS₁, MS₁₉ is generated via mixing MS₁ andMS₃, MS₁₁ is generated via mixing MS₁ and MS₄, MS₁₂ is generated viamixing MS₄ and DS₂.

In view of above-mentioned embodiments, the signal delay method shown inFIG. 8 can be obtained, which includes the following steps:

801

Utilize a first delay path, such as path 1 in FIG. 3, in the signaldelay circuit to delay the first input signal IN to generate a firstdelay signal DS₁.

803

Utilize a second delay path, such as path 2 in FIG. 3, to delay thefirst input signal to generate a second delay signal DS₂.

805

Mix the first delay signal DS₁ and the second delay signal DS₂ togenerate a first mixed signal MS₁.

Corresponding to the embodiment shown in FIG. 5, the signal delay methoddepicted in FIG. 8 further comprise: utilizing a third delay path, suchas the path passing through the third delay stage 405 in FIG. 5, todelay the first input signal IN to generate a third delay signal DS₃.Also, the third delay signal DS₃ can be utilized to mix with one of thefirst delay signal DS₁ and the second delay signal DS₂ to generate amixed signal.

Corresponding to the embodiment shown in FIG. 4, the signal delay methoddepicted in FIG. 8 further comprise: utilizing a fourth delay path, suchas the path passing through the fourth delay stage 407 in FIG. 4, todelay the first input signal IN to generate a fourth delay signal DS₄.The third and the fourth delay paths share at least one delay unit. Thethird delay signal DS₃ and the fourth delay signal DS₄ are mixed togenerate a second mixed signal MS₂, and the first mixed signal MS₁ canbe mixed with one of the third delay signal DS₃, the fourth delay signalDS₄ and the second mixed signal MS₂ to generate a new mixed signal.

Corresponding to the embodiment shown in FIG. 4, the signal delay methoddepicted in FIG. 8 further comprise: utilizing the fifth delay path,such as the path passing through the fifth delay stage 610 in FIG. 6, todelay a second input signal IN2 to generate a fifth delay signal DS₅;utilizing the sixth delay path, such as the path passing through thesixth delay stage 612 in FIG. 6, to delay the second input signal IN₂ togenerate a sixth delay signal DS6, wherein the fifth delay path and thesixth path share at least one delay unit; utilizing the seventh delaypath, such as the path passing by the seventh delay stage 614 in FIG. 6,to delay the second input signal IN₂ to generate a seventh delay signalDS₇; utilizing the eighth delay path, such as the path passing by theeighth delay stage 616 in FIG. 6, to delay the second input signal IN₂to generate a eighth delay signal DS₈, wherein the seventh delay pathand the eighth path share at least one delay unit. The signal delaymethod further comprises mixing the fifth delay signal DS₅ and the sixthdelay signal DS₆ to generate a fifth mixed signal MS₅ and mixing theseventh delay signal DS₇ and the eighth delay signal DS₈ to generate asixth mixed signal MS₆. The fifth mixed signal MS₅ can be mixed with oneof the seventh delay signal DS₇, the eighth delay signal DS₈ and thesixth mixed signal MS₆ to generate a new mixed signal.

In view of above-mentioned embodiments, the signal delay circuitaccording to the present invention can have smaller input and outputloading. Additionally, different mixed signals can be utilized toperform fine tune to obtain more accurate clock signals, besidesutilizing each delay Stage to perform coarse tune. Moreover, delay forcoarse tune and fine tune have better adjusting linearity since the samedelay stage(s) is/are utilized to perform both the fine tune and coarsetune.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A signal delay circuit, comprising: a first delaystage, for delaying a first input signal to generate a first delaysignal; and a second delay stage, for cooperating with part of delayunits of the first delay stage to delay the first delay signal togenerate a second delay signal; wherein the signal delay circuitselectively enables the delay units of the first delay stage or thesecond delay stage; and wherein the signal delay circuit mixes the firstdelay signal and the second delay signal to generate a first mixedsignal when the first delay stage and the second delay stage are bothenabled.
 2. The signal delay circuit of claim 1, wherein the signaldelay circuit utilizes a single output terminal to output the firstdelay signal, the second delay signal and the first mixed signal.
 3. Thesignal delay circuit of claim 1, wherein the first mixed signal has afirst mixed delay amount, which is larger than a first delay amount ofthe first delay signal and smaller than a second delay amount of thesecond delay signal.
 4. The signal delay circuit of claim 1, wherein thefirst delay stage has a first delay unit and a second delay unit, thesecond delay stage has a third delay unit, a fourth delay unit and afifth delay unit; wherein an input terminal of the first delay unit andan input terminal of the third delay unit receive the first inputsignal, an input terminal of the second delay unit receives an output ofthe first delay unit and an output of the fifth delay unit, an inputterminal of the fourth delay unit receives an output of the third delayunit, and an input terminal of the fifth delay unit receives an outputof the fourth delay unit.
 5. The signal delay circuit of claim 4,wherein the first delay signal is generated by delaying the first inputsignal via the first delay stage and the second delay stage, and thesecond delay signal is generated by delaying the first input signal viathe second delay stage, the third delay stage, the fourth delay stageand the fifth delay stage.
 6. The signal delay circuit of claim 1,further comprising a third delay stage, for cooperating with part ofdelay units of the first delay stage and the second delay stage, todelay the first input signal to generate a third delay signal, whereinthe signal delay circuit selectively enables the delay units of thethird delay stage; and wherein the signal delay circuit mixes the thirddelay signal and one of the first delay signal and the second delaysignal to generate a mixed signal when the third delay stage is enabled.7. The signal delay circuit of claim 1, further comprising a third delaystage, for delaying the first input signal to generate a third delaysignal, wherein the signal delay circuit selectively enables delay unitsof the third delay stage; and wherein the signal delay circuit mixes thethird delay signal and at least one of the first, the second delaysignals to generate a mixed signal when the third delay stage isenabled.
 8. The signal delay circuit of claim 7, wherein the third delaysignal includes a third delay amount, which is the same as one of afirst delay amount from the first delay signal and a second delay amountfrom the second delay signal, wherein the signal delay circuit generatesthe first delay signal if the third delay amount is the same as thefirst delay amount, the first and third delay stages are enabled but thesecond delay stage is disabled; and wherein the signal delay circuitgenerates the second delay signal if the third delay amount is the sameas the second delay amount, the second and third delay stages areenabled but the first delay stage is disabled.
 9. The signal delaycircuit of claim 7, further comprising a fourth delay stage, forcooperating with part of delay units of the third delay stage to delaythe first delay signal to generate a fourth delay signal, wherein thesignal delay circuit selectively enables the delay units of the fourthdelay stage; and wherein the third delay signal and the fourth delaysignal are mixed to generate a second mixed signal, and the first mixedsignal is mixed with one of the third delay signal, the fourth delaysignal and the second mixed signal to generate a new mixed signal whenthe third delay stage and the fourth delay stage are both enabled. 10.The signal delay circuit of claim 9, wherein the third delay signalincludes a third delay amount being the same as a first delay amountfrom the first delay signal, and the fourth delay signal includes afourth delay amount being the same as a second delay amount from thesecond delay signal; wherein the signal delay circuit generates thefirst delay signal if the first and third delay stages are enabled butthe second and fourth delay stage are disabled; and wherein the signaldelay circuit generates the second delay signal if the second and fourthdelay stages are enabled but the first and third delay stages aredisabled.
 11. The signal delay circuit of claim 9, further comprising: afifth delay stage, for delaying a second input signal to generate afifth delay signal; a sixth delay stage, for cooperating with part ofdelay units of the fifth delay stage to delay the second input signal togenerate a sixth delay signal; a seventh delay stage, for delaying thesecond input signal to generate a seventh delay signal; an eighth delaystage, for cooperating with part of delay units of the seventh delaystage to delay the second input signal to generate a eighth delaysignal; wherein the signal delay circuit selectively enables delay unitsof the fifth, the sixth, the seventh and the eighth delay stages;wherein the signal delay circuit mixes the fifth delay signal and thesixth delay signal to generate a fifth mixed signal if the fifth delaystage and the sixth delay stage are both enabled; wherein the signaldelay circuit mixes the seventh delay signal and the eighth delay signalto generate a sixth mixed signal if the seventh delay stage and theeighth delay stage are both enabled; wherein the fifth mixed signal ismixed with one of the seventh delay signal, the eighth delay signal andthe sixth mixed signal to generate a new mixed signal if the fifth, thesixth, the seventh and the eighth delay stages are all enabled.
 12. Asignal delay method, for a signal delay circuit including a first delaypath and a second delay path, wherein the first delay path and thesecond delay path share at least one delay unit, the signal delay methodcomprising: utilizing the first delay path to delay a first input signalto generate a first delay signal; utilizing the second delay path todelay the first input signal to generate a second delay signal; andmixing the first delay signal and the second delay signal to generate afirst mixed signal.
 13. The signal delay method of claim 12, wherein thefirst mixed signal has a first mixed delay amount, which is larger thana first delay amount of the first delay signal and smaller than a seconddelay amount of the second delay signal.
 14. The signal delay method ofclaim 12, wherein the signal delay circuit further comprises a thirddelay path, the signal delay method further comprising: utilizing thethird delay path to delay the first input signal to generate a thirddelay signal, wherein the first, the second and the third delay pathsshare at least one delay unit; and wherein the signal delay methodfurther comprises mixing the third delay signal and one of the firstdelay signal and the second delay signal to generate a mixed signal. 15.The signal delay method of claim 12, further comprising utilizing athird delay path to delay the first input signal to generate a thirddelay signal; wherein the signal delay method further comprises mixingthe third delay signal with at least one of the first delay signal andthe second delay signal to generate a mixed signal.
 16. The signal delaymethod of claim 15, wherein the signal delay circuit further comprises afourth delay path, the signal delay method further comprising: utilizingthe fourth delay path to delay the first input signal to generate afourth delay signal, wherein the third and the fourth delay paths shareat least one delay unit; and wherein the third delay signal and thefourth delay signal are mixed to generate a second mixed signal, and thefirst mixed signal is mixed with one of the third delay signal, thefourth delay signal and the second mixed signal to generate a new mixedsignal.
 17. The signal delay method of claim 16, wherein the signaldelay circuit further comprises a fifth delay path, a sixth delay path,a seventh delay path and an eighth delay path, wherein the signal delaymethod comprises: utilizing the fifth delay path to delay a second inputsignal to generate a fifth delay signal; utilizing the sixth delay pathto delay the second input signal to generate a sixth delay signal,wherein the fifth delay path and the sixth path share at least one delayunit; utilizing the seventh delay path to delay the second input signalto generate a seventh delay signal; utilizing the eighth delay path todelay the second input signal to generate a eighth delay signal, whereinthe seventh delay path and the eighth path share at least one delayunit; wherein the signal delay method further comprises mixing the fifthdelay signal and the sixth delay signal to generate a fifth mixed signaland mixing the seventh delay signal and the eighth delay signal togenerate a sixth mixed signal; and wherein the fifth mixed signal ismixed with one of the seventh delay signal, the eighth delay signal andthe sixth mixed signal to generate a new mixed signal.